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Branch prediction is critical to the instruction-level parallelism. Researchers have been focusing on branch direction algorithm for a long time and recent improvement on the prediction accuracy in literatures is achieved by increasing the complexity of algorithms and at the cost of enlarging the branch target buffers. Thus many of these high accuracy branch prediction approaches cannot be implemented in practice due to the boundary to access and high hardware cost. This paper proposes a hierarchical branch prediction architecture (HBPA), within which complex or time-consuming algorithms and overlarge branch target buffers are moved from the front-end of instruction pipeline to the write-back stage. HBPA speeds up the branch prediction thanks to the simpler front-end structure. Meanwhile a preferable algorithm and compatible buffers can be implemented in the hierarchical memory, which assures the feasibility of HBPA. Effectiveness of HBPA in terms of misprediction rate and IPC is measured and the results suggest a definite improvement on performance. In a word, the hierarchical branch predictor is novel, efficient and applicable to the current as well as future aggressive processors.