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This paper presents a new circuit technique to reduce temperature-induced delay uncertainty. Programmable temperature compensation devices (PTCDs) are used to tune logic gate pull-up and pull-down networks to their respective temperature-insensitive operating points, dramatically improving thermal resilience. Over a -55°C to 125°C temperature range, the proposed technique is shown to decrease temperature-induced delay uncertainty by up to 91% compared to other temperature resilient methods. We explore the limitations of using multi-VT and adaptive body biasing approaches to achieve temperature insensitivity; the proposed method achieves insensitive operation at larger supply voltages than prior methods, providing temperature insensitivity at nominal voltage for the first time. We explain how to integrate PTCDs into a variety of logic gates as well as larger structures such as a 1-bit mirror adder. Applying the proposed method to a clock tree is shown to reduce temperature-induced clock skew by up to 98%. Process variations degrade the temperature resilience; however, the proposed approach still improves temperature resilience by ~50% over prior methods when these variations are considered. Furthermore, we propose a process variation-compensation system to maintain our PTCD method's temperature resilience.