A structural approach for designing performance enhanced signal processors: a 1-MIPS GSM fullrate vocoder case study

Performance enhanced DSP (digital signal processor) architectures incorporate either datapath add-ons such as dual-MAC architectures or tailored datapaths such as Viterbi accelerators. Both strategies strongly influence the instruction set architecture (ISA). Since common ISAs are not designed for architectural enhancements, either a complete redesign is required or architectural enhancements cannot be fully exploited by the ISA. Taking the GSM fullrate vocoder as an example, a structural approach is presented to show how datapath add-ons or tailorizations can be applied to increase the DSP's performance. To efficiently utilize architectural enhancements we propose a modified VLIW (very long instruction word) ISA, called TVLIW (tagged VLIW). TVLIW combines both VLIW performance and DSP codewidth requirements. To demonstrate the applicability, we applied the TVLIW ISA to a highly pipelined quadruple-MAC architecture, incorporating only one dualport RAM and a 26-bit wide instruction word.