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A Comma Detection and Word Alignment Circuit for High-Speed SerDes

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2 Author(s)
Zhen Yu ; Inst. of RF-&OE-lCs, Southeast Univ., Nanjing, China ; Qing-sheng Hu

A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18 μm CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW under 1.8V power supply.

Published in:

Wireless Communications, Networking and Mobile Computing (WiCOM), 2011 7th International Conference on

Date of Conference:

23-25 Sept. 2011