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This paper introduces four path-based DVFS algorithms for embedded multimedia applications. Application model consists of multiprocessor scheduled task-graphs and input class probability distributions. Design constraints are a soft delay deadline and a minimum completion ratio. The algorithms target four scenarios that correspond to systems with various DVFS and quality of service monitoring capabilities. In the first scenario, all inputs must be timely processed, voltage/frequency level can be adjusted in the beginning of application execution and must be the same for all processors. In the second scenario, the voltage/frequency level of a processor can be individually adjusted when a task execution starts, inputs of particular classes can be discarded without processing. In the third scenario, a processor voltage can be adjusted to the class of the input received. The fourth scenario aims at compensating for online changes of input class distribution in a system with the same capabilities as required for the third scenario.
Date of Conference: Aug. 31 2011-Sept. 2 2011