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A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication

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4 Author(s)
Haoyuan Ying ; Darmstadt Univ. of Technol., Darmstadt, Germany ; Ashok Jaiswal ; Thomas Hollstein ; Klaus Hofmann

Today industry is moving towards Multi-Processor Systems on Chip (MPSoCs) to take advantage of available parallelism. But common bus architectures for MPSoCs are not suitable as communication infrastructures, due to significant reduction in system throughput. To solve this problem, many Networks-on-Chip (NoCs) architectures have been proposed and analyzed extensively with respect to latency, area and power. The congestion control in NoCs for best-effort communication has gained importance among designers because of the increasing traffic load demand. This paper presents a fast congestion-aware flow control mechanism for ID-Based NoCs with best-effort communication. The proposed method utilizes the combination of local and global control mechanisms, i.e. congestion information at the local node, where the congestion occurs, provides expected injection rates to the corresponding traffic sources. The experimental results indicate that this method can achieve approximately the same network throughput for different traffic scenarios (Hot Spot, Bit Complement and All2One). This method is at least 76% faster than the standard back-pressure mechanism in informing the sending source about the congestion problem in the network (Congestion-Aware Time). The method also shows at least 35% latency improvement (depending upon traffic scenarios) compared to standard back-pressure mechanism.

Published in:

Digital System Design (DSD), 2011 14th Euromicro Conference on

Date of Conference:

Aug. 31 2011-Sept. 2 2011