Referenced Items are not available for this document.
To achieve high-resolution in electrically noisy environments as well as low-power, we propose a differential capacitance-to-digital converter (CDC) that utilizes three-level time-domain manipulation of intermediate signals. The proposed CDC, designed in 0.35 μm digital CMOS technology and simulated with HSPICE, achieves a 9-bit resolution at the power supply of 3.3 V with the superimposition of 600 mVpp 2.5 kHz square-wave noise disturbance, consuming the average power of 158.3 μW/sample.
Published in:
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Date of Conference: 7-10 Aug. 2011
- Page(s):
- 1 - 4
- ISSN :
- 1548-3746
- E-ISBN :
- 978-1-61284-855-6
- Print ISBN:
- 978-1-61284-856-3
- INSPEC Accession Number:
- 12269432
- Conference Location :
- Seoul
- Digital Object Identifier :
- 10.1109/MWSCAS.2011.6026286
- Product Type:
- Conference Publications
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