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High speed CMOS vision chips

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1 Author(s)
Nanjian Wu ; State Key Lab. for Super Lattices & Microstructures, Chinese Acad. of Sci., Beijing, China

This paper presents novel high speed vision chips based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit. The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N×N) parallelism and an O(N) parallelism, respectively. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively. Prototype chips are fabricated using the 0.18μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.

Published in:

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

Date of Conference:

7-10 Aug. 2011