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The design of a fully integrated, filterless, class-D audio amplifier in standard 0.25- CMOS technology is described: a novel class-D amplifier architecture, where uniform pulsewidth modulation is introduced. The architecture attenuates residual clock signals around the loop allowing very low harmonic distortion, , to be achieved in conjunction with high PSRR, at 217 Hz. When driving 1.2 W into an 8- load, it achieves an SNR of 103 dB (A-weighted) with an efficiency of . The maximum output power at 1% THD is 3.1 W. Figures of merit are defined to establish that the amplifier exceeds the performance of alternative designs. The amplifier occupied a chip area 1.44 and was packaged as a WLCSP.