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In this paper, we propose a 3-stage framed packet switch using an internal speedup of 2 to avoid any control loop between any two stages of the switch. The switch segments the arriving variable-length packets at each input port into fixed-size cells and assembles the cells into frames. Then the frames are switched across the shared buffers to their destined output ports, and the cells are reassembled into packets before being transmitted to the next hop. We have designed a broad class of work-conserving scheduling algorithms for the proposed switch, and they are analyzed to be stable, i.e. achieving 100% throughput, under any admissible traffic. To gain more insights into the switch practical performance, an extensive performance evaluation study is conducted using computer simulations. Our results demonstrate that the worst-case performance can be bounded. In addition, we are able to achieve a high throughput-delay performance comparable to that of the padded frame switch which uses a much more complicated scheduling algorithm.