Tunnel FET-based pass-transistor logic for ultra-low-power applications

Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm L
G
. For low throughput applications (>100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.