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Study on nanoparticles embedded multilayer gate dielectric MOS non volatile memory devices

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2 Author(s)
Sengupta, A. ; Dept. of Electron. & Telecommun. Eng., Jadavpur Univ., Kolkata, India ; Sarkar, C.K.

In this paper we present a theoretical study on nanoparticles embedded, multilayer gate oxide, MOS non volatile memory devices. Two devices, one with a pure SiO2 tunnel oxide, and other with a stacked HfO2-SiO2 tunnel oxide were compared. The nanoparticles, were assumed embedded in a Si3N4 layer. Using Maxwell Garnett model and WKB approximation, the direct tunneling current and the I-V characteristics were simulated. The simulated Flatband voltage shift was compared with recent experimental results.

Published in:

Nanoelectronics Conference (INEC), 2011 IEEE 4th International

Date of Conference:

21-24 June 2011

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