Study on nanoparticles embedded multilayer gate dielectric MOS non volatile memory devices

In this paper we present a theoretical study on nanoparticles embedded, multilayer gate oxide, MOS non volatile memory devices. Two devices, one with a pure SiO
₂
tunnel oxide, and other with a stacked HfO
₂
-SiO
₂
tunnel oxide were compared. The nanoparticles, were assumed embedded in a Si
₃
N
₄
layer. Using Maxwell Garnett model and WKB approximation, the direct tunneling current and the I-V characteristics were simulated. The simulated Flatband voltage shift was compared with recent experimental results.