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Characterization and failure analysis of Sub-10 nm diameter, gate-all-around nanowire field-effect transistors subject to electrostatic discharge (ESD)

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6 Author(s)
Liu, W. ; Sch. of EECS, Univ. of Central Florida, Orlando, FL, USA ; Liou, J.J. ; Singh, N. ; Lo, G.Q.
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Electrostatic discharge (ESD) robustness of the Sub-10 nm diameter gate-all-around nanowire field-effect transistor (NW FET) was characterized and compared with sub 65nm MOS devices and FinFETs. Failure mechanisms of NW FETs subject to ESD stresses are investigated by DC current-voltage measurements carried out before and after stressing the devices with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester.

Published in:

Nanoelectronics Conference (INEC), 2011 IEEE 4th International

Date of Conference:

21-24 June 2011