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FPGA controller for rearrangeable Log2(N, 0, p) fabrics with an even number of stages

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2 Author(s)
Kabacinski, W. ; Dept. of Commun. & Comput. Networks, Poznan Univ. of Technol., Poznan, Poland ; Michalski, M.

In this paper we present rearrangeable log2(N, 0, p) switching fabrics and the control algorithm for the case of an even number of stages. The main topic of this paper is the implementation of a hardware controller for such fabrics. The algorithm is described in VHDL code and realized in ML505 - the demo board for Virtex 5 - FGPA chip from the Xilinx Company. The implementation presented here works very fast, the controller can send out the set of actual signals just 20 nanoseconds after the request has been made.

Published in:

High Performance Switching and Routing (HPSR), 2011 IEEE 12th International Conference on

Date of Conference:

4-6 July 2011