Cart (Loading....) | Create Account
Close category search window
 

PowerDepot: Integrating IP-based power modeling with ESL power analysis for multi-core SoC designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Chen-Wei Hsu ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Jia-Lu Liao ; Shan-Chien Fang ; Chia-Chien Weng
more authors

In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation formulation. By linking these two methods of different levels of abstraction, one can thereby easily profile the power consumption of a multi-core SoC running a complete application while retaining high accuracy of estimation. We have realized the proposed methodology into two software tools: (1) PowerMixerIP, an IP-based power model builder that uses different strategies to build versatile power models for general IPs and processor IPs, and (2) PowerDepot, an ESL power estimation tool that can interact with the users in a simple way and then generate the needed power monitors to be embedded into the ESL design in SystemC for super-fast power estimation so as to facilitate early-stage system-wide power profiling. The application of these tools on a dual-core real-life designs executing an H.264 shows that the average error of the ESL power estimation is less than 2%, while the speedup can be up to 2400X when comparing to gate-level simulation.

Published in:

Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE

Date of Conference:

5-9 June 2011

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.