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In this paper, a technique to reduce the output jitter and the wide-range operation is presented. A wide-range voltage controlled delay line (WRVCDL) uses multi-band to operate on wide-range. The proposed DLL operates from 25MHz to 250MHz. An edge combiner (EC) is used to increase the output frequency range. It synthesizes frequencies from 250MHz to 2.5GHz. The output of EC will be a 50% cycle in all different frequencies. The presented clock generator uses a dynamical phase detector (DPD) to effectively reduce the DLL output jitter from 7.81ps to 5.4ps at 250MHz. In simulation results which show the output jitter is from 16.2p to 11.7p at 2.5GHz by using the calibration. The static phase error of the proposed DLL reduced from 7.35ps to 2.1ps at 250MHz. The proposed DLL has been fabricated in 0.18μm 1P6M CMOS process. The total power consumption is 6.14mW in 2.5GHz with buffer and the core area is 0.033mm2.