Cart (Loading....) | Create Account
Close category search window
 

Robust Clock Network Design Methodology for Ultra-Low Voltage Operations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Mingoo Seok ; Syst. Archit. R&D Center at Texas Instrum., Dallas, TX, USA ; Blaauw, D. ; Sylvester, D.

Robust design is a critical concern in ultra-low voltage operation due to large sensitivities to process and environmental variations. In particular, clock networks require careful attention to ensure robust distribution of well-defined clock signals to avoid setup and hold time violations. In this paper, we propose two complementary methodologies to design robust and low power clock networks at ultra-low voltage regimes, an un-buffered and buffered approach, which can be chosen from depending on the significance of wire resistance. We confirm the efficacy of the proposed strategies through simulations with test circuits over different supply voltages, technologies, and design sizes. We also perform case studies of low voltage clock network design for a microprocessor and signal processing core. For one case study, we employ the un-buffered methodology, reducing +2 σ skew by ~ 5000 × and +2 σ slew by ~ 15% without energy overhead, compared to conventional 1-level buffered H-trees. In the other case, a 3-level buffered tree is implemented, with the proposed clock tree reducing +2 σ skew to ~ 2 % of a clock cycle ( 0.68 × fanout-of-4 delay) and slew variability (σ/μ) to 0.08 at V.

Published in:

Emerging and Selected Topics in Circuits and Systems, IEEE Journal on  (Volume:1 ,  Issue: 2 )

Date of Publication:

June 2011

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.