Dynamic partial reconfiguration of 2-D Haar wavelet transform (HWT) for face recognition systems

This paper presents two novel architectures for two-dimensional (2-D) Haar wavelet transform (HWT) of transform block in face recognition systems. The proposed architectures comprises 2-D HWT with transpose-based computation and dynamic partial reconfiguration (DPR) that have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. To evaluate the proposed architecture, comparison for both configurations and a detailed performance analysis in terms of area, power consumption and maximum frequency are also addressed in this paper.