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Cyclo-inverters are ideal for induction heating and melting applications. The direct power conversion in a cyclo-inverter however causes, unfortunately, distortion currents in the input lines and the output circuit. In this paper an attempt has been made to minimize these undesirable components using trapezoidal pulse width modulation technique and implementing it on FPGA. Peripheral input-output and FPGA interfacing has been developed through Xilinx 9.2i to generate Trapezoidal PWM trigger signal for the cyclo-inverter. To relieve the controller from the time consuming computational task of PWM signal generation, Very Hardware Description Language VHDL has been used in Xilinx. The trigger circuit has been tested qualitatively by observing various triggering pulses on Modelsim XE III 6.2g. The operation of proposed system has been found satisfactory.