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Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications

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5 Author(s)
Jinn-Shyan Wang ; Dept. of Electr. Eng., Nat. Chung-Cheng Univ. (CCU), Chiayi, Taiwan ; Pei-Yao Chang ; Tai-Shin Tang ; Jia-Wei Chen
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The design of embedded subthreshold SRAMs for a quality-scalable H.264 video decoder IP is presented in this paper. In addition to the conventional 7T SRAM bitcell, we adopted power-gating techniques and multi-output dynamic circuits in order to achieve a low VDDmin, a small area overhead, and a higher operating speed. A 256 × 32 90-nm SRAM macro was designed for verifying the proposed design techniques. The H.264 IP provides energy-efficient scalable video decoding of 42.8 pJ/cycle for QCIF and 235 pJ/cycle for HD720 at 0.3 V and 0.7 V, respectively.

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Emerging and Selected Topics in Circuits and Systems, IEEE Journal on  (Volume:1 ,  Issue: 2 )