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The scaling of IC feature sizes has increased the integration capability and allowed the design of large systems in one single chip. This improvement has also contributed to reconfigurable circuits densities, such as the Xilinx Virtex-4 FPGA, which exceeds ten million gates. In spite of that, circuit miniaturization will also increase defect and fault rates in such high magnitude that a fault tolerance approach will be mandatory for the proper functioning of any circuit in future technologies. To cope with manufacturing defects and permanent faults in FPGAs, this paper presents an approach that dynamically instantiates the resources in non-faulty regions of the FPGA. The run-time control system works around the faulty FPGA region and instantiates the logic and routing units in non-faulty ones. This allows one to sustain performance by preserving the amount of resources. Moreover, the proposed fault tolerance approach is transparent to the user. For each configuration the control system automatically instantiates the units according to the application's data flow graph and the defect and fault map.
Date of Conference: 6-9 June 2011