By Topic

Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Bauer, L. ; Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany ; Shafique, M. ; Henkel, J.

This paper describes an approach that allows using the potential of reconfigurable processors in an efficient and adaptive manner. Some architectural design decisions (e.g., the provided memory interface, number of ports, and bit-width per port) have a strong impact on the efficiency, whereas other design decisions (e.g., how the reconfigurable fabric is used to implement application-specific accelerators) have an impact on the adaptivity that the reconfigurable processor can provide. Therefore, we will present and discuss different design decision alternatives for reconfigurable processor architectures. After introducing the basic concepts and principal advantages of reconfigurable processors, the promising concept of modular Special Instructions (SIs) is presented as a general approach to achieve a high adaptivity in reconfigurable processors. This paper shows how these modular SIs can be used to achieve high adaptivity and which scenarios benefit from such adaptive processing behavior. Afterwards, the basic requirements and infrastructure to operate modular SIs in an efficient and adaptive manner are presented in detail and analyzed. To exploit the adaptivity that is provided by modular SIs, a run-time system is required to decide how the reconfigurable processor shall react on changing requirements and situations. This paper gives a general overview of the steps that need to be performed by such a run-time system. Finally, the adaptive reconfigurable RISPP processor that is based on the presented architectural design decisions, the concept of modular special instructions, and the controlling run-time system is evaluated.

Published in:

Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on

Date of Conference:

6-9 June 2011