A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS

A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller, with no need for a highly linear feedback D/A converter. The TC-ADC embeds its own references, and relies on a minimal amount of passive components or calibration loops. A 6-bit prototype implementation in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s and consumes 240 μW from 1-V analog and 0.7-V digital supplies. This results in 150 fJ/conversion-step in a core area occupation of only 0.0055 mm .