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Performance enhancement of modified turbo codes with two-stage interleavers

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2 Author(s)
A. Bhise ; Department of Electronics and Telecommunication Engineering, K. J. S. Institute of Engineering and Information Technology, Sion, Mumbai, India ; P. D. Vyavahare

Low complexity modified turbo codes (MTC) offer bit error rate performance close to Shannon's limit with significantly reduced decoding complexity. However, since interleavers used in turbo codes interleave bit positions in one-dimensional (1D) array, they cannot be used for MTC which encode information bits arranged in 2D array. Moreover, MTC use several interleavers which increase the memory requirement to store permutation patterns. Objective of this study is to design two-stage interleaver for MTC with low memory requirement, large values of column spreading factor and dispersion in the interleaved pattern. Expressions have been derived for limits on maximum values of spreading factor and dispersion for 2D information array. Simulation results show superior performance of MTC with two-stage interleavers than that with random interleavers at high bit energy to noise ratio. Moreover, analysis shows that two-stage interleaver requires 50' less memory storage than random interleaver. Proposed interleaver can also be used for turbo codes in which 1D information array is being used.

Published in:

IET Communications  (Volume:5 ,  Issue: 10 )