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In this paper an ultra low power SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current, a dual-stage (Resistor-string / capacitive dividing) architecture as digital-to-analog converter (DAC) and using subthreshold design with the aid of low supply voltage of 0.7v for DAC and 0.5v for SAR block and Pulse Generator Circuit (PGC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduce the silicon area significantly. A new FOM is also proposed for better verification of ADCs with power in μW and nW range. The circuit designed in 0.18um CMOS technology and post layout simulations show that the 8-bit core ADC, consumes almost 78.4nW at 17.8kS/s speed and the PGC block which is designed in subthreshold region consumes 84.1nW. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterparts.