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Fault Tolerant Computing Paradigm for Random Molecular Phenomena: Hopfield Gates and Logic Networks

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4 Author(s)
Tran, A.H. ; Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada ; Yanushkevich, S.N. ; Lyshevski, S.E. ; Shmerko, V.P.

This paper contributes to robust fault-tolerant computing for expected nano-centric processing hardware. We developed (a) techniques for fault tolerant logic network design given a library of AND, OR, NAND, and NOR Hop field gates, and (b) report experimental results on fault tolerant properties of designed networks. In particular, several hundred iterations are required to achieve correct outputs in a five-input single-output networks in the presence of 40% noise.

Published in:

Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on

Date of Conference:

23-25 May 2011