By Topic

A Graph-Based Approach to Designing Multiple-Valued Arithmetic Algorithms

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Saito, K. ; Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; Homma, N. ; Aoki, T.

This paper presents a graph-based approach to designing multiple-valued arithmetic circuits. Our method describes arithmetic circuits in a hierarchical manner with high-level multiple-valued graphs, which are determined by specific algebra and arithmetic formulae. The proposed circuit description can be effectively verified by symbolic computations such as polynomial reduction using Groebner Bases. In this paper, we describe the proposed graph representation and show an example of its description and verification. The advantageous effects of the proposed approach are demonstrated through experimental designs of parallel multipliers over Galois field GF(2m) for different word-lengths and irreducible polynomials. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits where the conventional simulation techniques failed.

Published in:

Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on

Date of Conference:

23-25 May 2011