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The CMOS image sensors are achieving a growing presence in today's mobile applications as the industry acknowledges the advances of the CMOS-based technology and its scaling possibilities. The roadmap recently unveiled for CMOS Image Sensor is announcing ever smaller pixels, after 1.4μm pixel pitch, demos with a pitch of 1.1μm were presented, and it also announces the future generation of pixels with 0.9μm pixel size. This steady decrease in pixel size has had a profound impact on sensors analog readout electronics, and, in particular, on their ADC architecture. For mobile applications, the ADCs are mostly placed in each column of image arrays, as the width of each converter need to fit in the image array pitch. The design becomes a true challenge as the available area for layout is very critical. To overcome this limitation, a compromise between column level and chip level ADCs can be used. A solution using a converter per 32 columns of the pixel array is proposed. The converter is a Successive Approximation (SA) ADC of apparent resolution 12 bits and is obtained from a 9 bits converter. This work presents a conversion architecture, particularly well adapted to image sensors where the noise level varies along with the amplitude of the useful signal. The proposed design presents the benefit of increasing the number of bits of the ADC without excessively increasing its complexity or its processing time. The converter is designed in CMOS 65nm technology, and will be implemented in a 5Megapixel sensor, at a sampling rate of 8.33MS/s. The simulations show good linearity and verify the concept of the new architecture.