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This work discusses the modeling of memristive devices, for architectures where they are used as synapses. It is shown that the most common models used in this context do not always accurately reflect the actual behavior of popular devices in pulse regime. We introduce a new behavioral model, intended towards the nanoarchitecture community. It fits the conductance evolution of Univ. Michigan's synaptic memristive devices. A variation of the model fits HP labs's memristors' behavior in the same conditions. Finally, we discuss using a simple example the importance of this type of modeling for learning architectures and how it can impact the behavior of the learning.