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Self-timed nano-PLA

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2 Author(s)
Zamani, M. ; Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Tahoori, M.B.

Emerging molecular based nanoelectronics is a promising alternatives for current CMOS technology to reduce manufacturing costs and achieve higher levels of integration. Extreme parameter variations resulted from nondeterministic nanofabrication can seriously affect the correct functionality and performance of circuits implemented in this technology. In this paper, we introduce modifications to nano-PLA, a major nano-architecture, to immune it against extreme variations by using self-timed local control signaling within the blocks instead of external global signals. Extensive Monte Carlo simulations for delay variations on a set of benchmarks confirms that the circuits implemented on the proposed architecture are 100% immune against delay variation, compared to only 37% for those circuits implemented on the original nano-PLA architecture. Moreover, the proposed architecture results in 47% reduction, in average, in critical path delay of mapped circuits.

Published in:

Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on

Date of Conference:

8-9 June 2011