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Scalability and design-space analysis of a 1T-1MTJ memory cell

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6 Author(s)
Richard Dorrance ; Department of Electrical Engineering, University of California, Los Angeles, USA ; Fengbo Ren ; Yuta Toriyama ; Amr Amin
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This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.

Published in:

2011 IEEE/ACM International Symposium on Nanoscale Architectures

Date of Conference:

8-9 June 2011