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This paper presents the characterization and design of a Static Random Access Memory (SRAM) cell at nano scale ranges. The proposed SRAM cell incorporates a Single-Electron (SE) turnstile and a Single-Electron Transistor (SET)/MOS circuit in its operation, hence its hybrid nature. Differently from previous cells, the hybrid circuit is utilized to sense (measure) on a voltage-basis the presence of at least an electron as stored in memory, while the turnstile enables the single electron transfer in and out of the storage node. The two memory operations (read and write) are facilitated by utilizing these hybrid circuits; moreover the proposed SRAM cell shows compatibility with MOSFET technology. HSPICE simulation shows that the proposed SRAM cell operates correctly at 45 and 32 nm with good performance in terms of propagation delay, signal integrity, stability and power consumption.
Date of Conference: 8-9 June 2011