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In this paper, we investigate the opportunity to use ultra-fine grain logic cells to design reconfigurable circuits. We use ultra-fine grain computation cells, built with only 7 Double-Gate Carbon Nanotubes FETs, and we arrange them into regular matrices with a fixed and incomplete interconnection pattern, in order to minimize the reconfigurable interconnection overhead. We subsequently organize them into Field-Programmable Gate Arrays (FPGAs) suited to ultra-fine grain reconfigurability. To assess this architectural scheme in an efficient and objective manner, we propose a complete benchmarking tool flow, which enables the optimization of the specific interconnection topologies. We finally perform the evaluation with widely used circuit benchmarks, and we show that the matrices have an optimal size of 3 by 3, while the ultra-fine grain FPGA demonstrated an area saving of up to 62% with respect to the CMOS LUT FPGA counterpart.
Date of Conference: 8-9 June 2011