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Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs)

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12 Author(s)
Hyoung Joon Kim ; Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore ; Ser Choong Chong ; Ho, D.S.W. ; Yong, E.W.Y.
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In this paper, we focus how to overcome process challenges, such as die shift and warpage, and to fabricate thin embedded wafer level packages (EMWLPs) with 200 μm-thick eventually. The initial warpage of reconfigured wafer after post mold curing (PMC) was about 1.0 ~ 1.4 mm range. After PMC, the molded wafer was background to 200 μm thickness and redistribution layer (RDL) process was conducted on both front- and back-sides of the molded wafer sequentially. However, the warpage increased up to several mm during 1st RDL formation so that multi-RDLs process could not be performed due to the largely warped wafer. In order to overcome the large warpage issue, thick Si wafer was adopted as a carrier and the molded wafer was bonded on the Si carrier before RDL process. The measured warpage values decreased from several mm to about 500 μm during RDL process by using the Si carrier and two RDLs were fabricated on both sides of the molded wafer. Consequently, the fabrication of 200 μm-thick molded wafer for EMWLPs was successfully achieved. Three reliability tests (MSL3, HAST, and TC) were performed with singulated EMWLP modules and no failure was observed in the results of component level reliability. Furthermore, for in-depth understanding of the effects of MCs and carrier types on the die shift of the reconfigured wafer, the die shift values were measured on the molded wafers made of different MCs and different carriers as well. The experimental results are being compared with computational simulation and this can provide basic guidance of material selection and molding process.

Published in:

Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st

Date of Conference:

May 31 2011-June 3 2011