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System in wafer-level package technology with RDL-first process

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9 Author(s)
Norikazu Motohashi ; Renesas Electronics Corporation, 1120, Shimokuzawa, Chuou-ku, Sagamihara, Kanagawa, Japan ; Takehiro Kimura ; Kazuyuki Mineo ; Yusuke Yamada
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We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication by using die-to-wafer (D2W) bonding with fine-pitch reflow soldering and simultaneous molding/underfilling at the wafer level.

Published in:

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

Date of Conference:

May 31 2011-June 3 2011