Referenced Items are not available for this document.
We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication by using die-to-wafer (D2W) bonding with fine-pitch reflow soldering and simultaneous molding/underfilling at the wafer level.
Published in:
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Date of Conference: May 31 2011-June 3 2011
- Page(s):
- 59 - 64
- ISSN :
- 0569-5503
- E-ISBN :
- 978-1-61284-496-1
- Print ISBN:
- 978-1-61284-497-8
- INSPEC Accession Number:
- 12071145
- Conference Location :
- Lake Buena Vista, FL
- Digital Object Identifier :
- 10.1109/ECTC.2011.5898492
- Product Type:
- Conference Publications
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