By Topic

Issues on short circuits in large on-chip power MOS-transistors using a modified checkerboard test structure

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hess, C. ; Inst. of Comput. Design, Karlsruhe Univ., Germany ; Weiland, L.H. ; Bornefeld, R.

To control random quality deviation of large on-chip power MOS-transistors, we have developed a modified checkerboard test structure. Using this structure, the complete chip area is divided into distinguishable subchips, each containing one large area power MOS-transistor. The fast digital measurements and the precise localization of transistor short circuits guarantee a fast process classification and enable additional electrical and optical defect parameter extraction

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997