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Design and characterization of SiGe TFT devices and process using Stanford's test chip design environment

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5 Author(s)
M. V. Kumar ; Center for Integrated Syst., Stanford Univ., CA, USA ; V. Subramanian ; K. C. Saraswat ; J. D. Plummer
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Stanford's test chip environment has been used to rapidly prototype a SiGe TFT process. The environment selected test structures tailored for the device/process. Then, with minimal effort and using parameterized test structures, the designer assembled a diagnostic test module. This module was used successfully in the development and optimization of the process, leading to the fabrication or high performance SiGe TFTs

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997