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An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

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6 Author(s)
J. C. Chen ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; D. Sylvester ; C. Hu ; H. Aoki
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In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3D simulations

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997