By Topic

A compact monitoring circuit for real-time on-chip diagnosis of hot-carrier induced degradation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
H. Oner ; Dept. of Electr. & Electron. Eng., Istanbul Tech. Univ., Turkey ; B. Bayrakci ; Y. Leblebici

A very simple test/monitor circuit is presented which emulates the hot-carrier induced degradation of those critical circuits which are most susceptible to hot-carrier induced aging in a large system on chip. Delay-time degradation, as opposed to current degradation, is devised as a more realistic measure for monitoring long-term circuit reliability, and a simple method is presented for measuring this degradation. The hot-carrier aging monitor is capable of issuing a warning signal (flag) when the amount of hot-carrier induced transient performance degradation in critical circuits on the chip exceeds a pre-determined limit value. The monitor circuitry occupies a very small silicon area; and it can be added to any large-scale design with a minimum of extra cost, at the end of the design cycle

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997