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Bundled data asynchronous multipliers with data dependent computation times

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2 Author(s)
D. Kearney ; Sch. of Phys. & Electron. Syst. Eng., South Australia Univ., SA, Australia ; N. W. Bergmann

A novel asynchronous design method is introduced which combines the area efficiency of bundled data with data dependent computation time. The design of a 16×16 bit multiplier using this technique is explained and evaluated. Simulation results show that area time savings of 20% compared to an equivalent synchronous design can be achieved

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on

Date of Conference:

7-10 Apr 1997