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SRAM bitline circuits on PD SOI: advantages and concerns

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8 Author(s)
J. B. Kuang ; Microelectron. Div., IBM Corp., Hopewell Junction, NY, USA ; S. Ratanaphanyarat ; M. J. Saccamango ; L. L. -C. Hsu
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This paper presents a study of sub-0.25-μm CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles. Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations

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IEEE Journal of Solid-State Circuits  (Volume:32 ,  Issue: 6 )