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A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

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13 Author(s)
T. Takeshima ; NEC Corp., Kanagawa, Japan ; M. Takada ; H. Koike ; H. Watanabe
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A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm2 chip area was attained by implementing 4.05-μm2 storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm2 and the area overhead is about 1%, it proves to be promising for large-scale DRAMs

Published in:

IEEE Journal of Solid-State Circuits  (Volume:25 ,  Issue: 4 )