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Performance analysis using a non-invasive instruction trace mechanism

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2 Author(s)
P. A. Sandon ; IBM Corp., Essex Junction, VT, USA ; Yuchung Liao

NStrace is a bus-driven hardware trace facility developed for the PowerPC family of super-scalar RISC microprocessors. It uses a recording of activity on a target processor's bus to infer the sequence of instructions executed during that recording period. The instruction sequence is generated by simulating the processor using an architectural simulator. It represents the behavior of the processor as it executes at normal speed while interacting normally with its runtime environment. We have traced applications on several systems, including one multiprocessor system, and running either AIX or Windows NT. The length of the trace is application dependent, but can range from 80 to over 100 million instructions. Trace records contain instructions and data, real and effective memory addresses, and timing information. We have developed several analysis tools to take advantage of the information provided by the combination of this rich trace format and the corresponding bus transactions

Published in:

Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International

Date of Conference:

5-7 Feb 1997