Cart (Loading....) | Create Account
Close category search window
 

Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Na Gong ; SUNY - Univ. at Buffalo, Buffalo, NY, USA ; Sridhar, R.

The leakage current characteristics of wide dual Vt domino OR gates is studied and gate-level models for estimating sub-threshold leakage and gate leakage current with two different sleep states are developed to determine the optimal sleep state. Results demonstrate that the developed models are robust and exhibit maximum error of 4% with respect to device-level BSIM4 models based HSPICE simulations. Furthermore, PVT variation aware leakage current characteristics of domino OR gates is analyzed and the optimal sleep state is obtained.

Published in:

SOC Conference (SOCC), 2010 IEEE International

Date of Conference:

27-29 Sept. 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.