Characterization and challenge of TDDB reliability in Cu/low K dielectric interconnect

Interconnect dielectric reliability challenges increase every generation due to dimension scaling and pursuing of lower K dielectrics for performance. In this paper, TDDB reliability characteration, process innovation, process control and product validation are presented based on Intel 32 nm technology node. In definition and technology development phase, extensive characterization and process innovation are needed to enable the proper choices of materials and processes. For any given healthy process and material set, the TDDB reliability is determined by via to line and line to line space distribution, and dominated by the tail distribution of dies with small space. Although different TDDB physical models such as E, root E or other models will project very different failure probability when extrapolating from high Efield to low Efield for the main population, the choice of models makes little difference for product level failure probability from the tail population because the Efield is already in the range of that used for accelerated stressing. Since product failure rate is dominated by tail population, more focus has been given to this area in terms of process development and control. Novel self-aligned via patterning process has been developed for 32 nm technology and significantly improved via to line space and thus the low K TDDB performance. In addition, to ensure superior quality and reliability, extensive process window and product level validation through extended life test are necessary to capture and eliminate worse case process and product corners. A scaling trend and potential path to enable continuing scaling are highlighted.