Referenced Items are not available for this document.
In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72μW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9μW.
Published in:
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Date of Conference: 25-28 April 2011
- Page(s):
- 1 - 4
- ISSN :
- Pending
- Print ISBN:
- 978-1-4244-8500-0
- INSPEC Accession Number:
- 12035432
- Conference Location :
- Hsinchu
- Digital Object Identifier :
- 10.1109/VDAT.2011.5783586
- Product Type:
- Conference Publications
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