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Through-Silicon Via (TSV) is a promising technology to reduce the length of interconnect in a three dimensional integrated circuit (3D-IC). However, the area overhead of TSV also poses a negative impact on a 3D-IC. Using too many TSVs will increase the die size and cancel out the benefit brought by TSV. Therefore, in this paper we will analyze the trade-off among wirelength and the number of TSVs with different TSV sizes. Since the number of TSVs is determined by placement, we also investigate how placement affects the wirelength and the number of TSVs. The experimental result shows that, in our study cases, the average maximum TSV area is 25.30% of the cell area. Beyond this value, virtually no wirelength reduction can be obtained.