Skip to Main Content
Functional verification of modern digital designs is a mission critical and time-consuming task. Verification is essential since it ensures the correctness of the final product; however, due to the complexity of modern designs, verification has become the primary bottleneck of time to market. Logic simulation forms the core of most current verification efforts, as it is almost ubiquitously used to verify the functional correctness of a design over a broad range of abstraction levels. In particular at the gate-level granularity, a design consists of millions of logic primitives, thus making simulation excruciatingly slow. In mainstream industry setups, complex digital systems are validated by distributing logic simulation tasks among vast server farms for weeks at a time. Yet, the performance of simulation keeps falling behind the demand, leading to incomplete verification and escaped functional bugs. It is no surprise that the EDA and semiconductor industries are always seeking for faster simulation solutions. Recently, advances in graphic processing unit (GPU) technology has made GPUs emerge as a cost effective parallel processing solution. Modern GPUs offer vast execution parallelism, which is a natural fit for the inherent parallel structure of gate-level netlists. Based on these observations, we propose novel algorithms for the efficient mapping of large netlists to the concurrent architecture of GPU hardware. Our GCS simulation architecture maximizes the utilization of concurrent hardware resources, while minimizing expensive communication overhead using a novel hybrid simulation method. Experimental results indicate that our GPU-based gate-level simulator delivers an order-of-magnitude performance improvement, on average, over commercial simulators on industrial-size designs.