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A DDR3 memory based time interleaving FPGA implementation for ISDB-T standard

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3 Author(s)
Edgardo J. Marchi ; Communications Laboratory, National Institute of Industrial Technology, Buenos Aires, Argentina ; Marcos A. Cervetto ; Marcelo L. Tenorio

The ISDB-T standard for digital broadcasting incorporates an extensive signal processing scheme in order to achieve reliable data integrity at the remote receiver. Particularly, the time interleaving stage requires a significant memory depth. Common implementations are often based in single-address access memories, which simplifies the algorithm logic but does not provide a cost-effective solution. This paper presents a DDR3 memory based FPGA implementation of the ISDB-T time interleaving stage. Widely available on the market for a broad type of applications, this kind of memory allows high data throughput and represents a low cost alternative. However, data must comply with a special structure and signalling since the memory access is burst-oriented. Consequently, the complexity is increased. The proposed design is both area-efficient and highly reconfigurable.

Published in:

Programmable Logic (SPL), 2011 VII Southern Conference on

Date of Conference:

13-15 April 2011