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This paper presents the design and implementation of finite Radon transform (FRAT) on field programmable gate array (FPGA). To improve the implementation time, Xilinx AccelDSP, a software for generating hardware description language (HDL) from a high-level MATLAB description has been used. FPGA-based architectures with three design strategies have been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)-based approach. Various medical images modalities have been deployed for both software simulation and hardware implementation. An analysis on the image de-noising using the FRAT is addressed and demonstrates a promising capability for medical image de-noising. Moreover, the impact of different block sizes on reconstructed images has been analysed. Furthermore, performance analysis in terms of area, maximum frequency and throughput is presented and reveals a significant achievement.
Date of Conference: 6-9 Dec. 2010